Not applicable.
Not applicable.
This invention is in the field of electronic circuits, and is more specifically directed to input circuits for receiving communicated signals.
Especially with the increasing deployment of wireless communications and data processing systems, many modern electronic systems and their integrated circuits are now battery powered. In order to save power, and thus prolong battery life, these circuits and systems are designed to use low bias voltages, and also to use small voltage levels for their analog and digital signals.
However, some high voltage signals are often still required in these low voltage systems, for various reasons. It is therefore important to provide the capability for certain low voltage circuits in these systems to be able to receive and process signals at voltages that are in excess of their bias voltage.
FIG. 1 illustrates an example of a conventional low voltage circuit that receives a high voltage signal for processing. According to this example, a multiple-input charge redistribution analog-to-digital converter (ADC) is provided by multiplexer 10 in combination with ADC 12. Multiplexer 10 receives the multiple analog input signals on lines BDATA, and IN(1) through IN(N). One of these inputs is selected by multiplexer 10 according to a selection signal on bus SEL, and is applied via line MUXOUT to an input of ADC 12. ADC 12, in turn, converts the analog signal selected by multiplexer 10 and presented on line MUX OUT into a digital signal, and forwards this signal on bus DOUT.
In this example of FIG. 1, however, multiplexer 10 is biased by power supply voltage AVDD, which may be a relatively low voltage, such as 2.75 volts derived from the output of a battery (not shown). Also in this example, input analog signals IN(1) through IN(N) have a voltage range from ground to voltage AVDD; however, input analog signal BDATA in this example can range to a much higher voltage than voltage AVDD, for example up to as high as 5.5 volts. This excessive input voltage on line BDATA presents a problem, particularly in the case where multiplexer 10 is constructed according to conventional techniques, such as a complementary metal-oxide-semiconductor (CMOS) pass gate, as will now be described relative to FIG. 2.
FIG. 2 illustrates multiplexer stage 10(0), which is effectively a pass gate associated with the BDATA input, controlled by a decoded select signal SEL(0) that is decoded from the selection signal on bus SEL. Such multiplexer construction is typical in the art, particularly for low voltage, low power, battery powered circuits that take advantage of the low standby power of CMOS technology. The pass gate of multiplexer stage 10(0) consists of n-channel MOS transistor 8N and p-channel MOS transistor 8P, which have their source-drain paths connected in parallel with one another between input BDATA and output MUXOUT. Transistors 8N, 8P have their gates controlled by the decoded signal on line SEL(0), directly in the case of transistor 8N and via inverter 9 in the case of transistor 8P. Inverter 9 is based by the low-voltage power supply voltage AVDD, and as such the gate voltages applied to the gate of transistor 8P will, in the digital sense, be either substantially at ground (input BDATA selected) or at voltage AVDD (input BDATA not selected).
In this example, the voltage of the analog input signal on line BDATA may exceed the voltage AVDD, in the case with input BDATA not selected. As noted above, inverter 9 applies a gate voltage of voltage AVDD to the gate of transistor 8P in the non-selected case. However, even with input BDATA not selected, transistor 8P will conduct if the voltage of the signal on line BDATA is higher than voltage AVDD by more than the threshold voltage of transistor 8P. In this case, the signal BDATA will be passed to output MUXOUT even though multiplexer 10 is not selecting this input. This event will cause multiplexer 10 to effectively pass two signals, only one of which is intended. This will, of course, present an erroneous voltage to the input of ADC 12 and result in an erroneous digital output on bus DOUT.
To alleviate his situation, conventional circuits have xe2x80x9cclippedxe2x80x9d the signal on input BDATA prior to its application to multiplexer 10, to reduce its voltage range to below bias voltage AVDD. Various conventional signal clipping approaches are well-known. One example of such a clipping circuit is simply to clip the signal with a simple resistor-diode network; however, this arrangement loads line BDATA if the input voltage causes the diode to conduct. In addition, the maximum signal voltage is necessarily reduced by a diode drop in this clipping circuit. If one were to buffer the signal on line BDATA with a voltage follower prior to the resistor-diode clipping circuit, the load on line BDATA would be reduced, at a cost of increased standby power, which is of course highly undesirable in battery-powered systems. Another approach is to insert a comparator and multiplexer to sense the high voltage input condition and to substitute the AVDD voltage as the input, at a cost of significant circuit complexity.
It is therefore an object of the present invention to provide a clipping circuit for processing a high voltage signal prior to its application to circuitry biased by a lower power supply voltage.
It is a further object of the present invention to provide such a circuit in which no additional loading on the high voltage signal is applied by the circuit.
It is a further object of the present invention to provide such a circuit which dissipates little or no power supply current.
It is a further object of the present invention to provide such a circuit which itself is biased by the lower power supply voltage.
It is a further object of the present invention to provide such a circuit which may be efficiently implemented into an integrated circuit.
It is a further object of the present invention to provide such a circuit having stable operating characteristics over a wide range of manufacturing process parameters.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with its drawing.
The present invention may be implemented into a clipping circuit including a current mirror-like clipping circuit. The current mirror has a reference leg biased between a source of limiting current and a lower power supply voltage at which downstream circuitry is biased. The current source may be a conventional current source biased from a higher voltage, or alternatively may be a charge pump circuit. Typically, the reference leg includes an n-channel MOS transistor that conducts a DC or pulsed bias current. The mirror leg, including an n-channel MOS device matched to that in the reference leg, is connected between a high voltage input node, and the output of the clipping circuit. In operation, the reference leg maintains the gate voltage of the nMOS device in the mirror leg at a level that briefly passes an input voltage that exceeds the power supply voltage, but then cuts off. The load presented by the clipping circuit is merely that of a single MOS device.